1. Field of the Disclosure
In general, the present disclosure relates to a method of forming a memory device structure and to a memory device structure, and, more particularly, to the formation of memory device structures including magnetic random access memory techniques at advanced technology scales, such as 40 nm and beyond.
2. Description of the Related Art
At present, semiconductor and magnetic storage technologies represent some of the most commonly used data storage technologies. Semiconductor memory uses semiconductor-based circuit elements, such as transistors or capacitors, to store information, and common semiconductor memory chips may contain millions of such circuit elements. Both volatile and non-volatile forms of semiconductor memory exist. In modern computers, primary storage almost exclusively consists of dynamic volatile semiconductor memory or dynamic random access memory (DRAM). Since the turn of the century, a type of non-volatile semiconductor memory known as flash memory has steadily gained share as off-line storage for home computers. Non-volatile semiconductor memory is also used for secondary storage in various advanced electronic devices and specialized computers.
In magnetic memory, information is stored by using different patterns of magnetization in magnetic layers, films or surfaces. As opposed to DRAM, magnetic storage is non-volatile and earlier implementations of magnetic storage made use of one or more read/write heads which may contain one or more recording transducers for accessing information stored in magnetically coated surfaces, where the read/write head only covered a part of the surface so that the head or medium or both move relative to another in order to access data.
A concept that may be considered as uniting DRAM and magnetic memory techniques is the so-called magnetoresistive random-access memory (MRAM). A memory cell of an MRAM type is similar in design to a memory cell of a DRAM type, but differs in that MRAMs employ magnetic storage elements for storing information instead of storing information as electric charge on a capacitor as is the case in DRAM cells. Therefore, unlike DRAMs losing their charge over time, MRAMs represent non-volatile memory devices that do not have to refresh memory cells of memory chips by reading each single memory cell and rewriting the content of each single memory cell as is the case in DRAM technologies.
This has an important impact on future developments. For example, when considering memory devices of the next generation, that is, at technology nodes of 40 nm and beyond, e.g., at 28 nm and beyond, a scaling of DRAM cells requires a more frequent refreshing of the individual memory cells, resulting in greater power consumption of DRAM memory structures. In contrast, an MRAM cell never requires a refresh, but retains its memory even when the power is turned off as there is no constant power draw necessary for storing data in MRAM memory devices.
It is also worth comparing MRAM with another common memory system, flash RAM. Like MRAM, flash does not lose its memory when power is removed, which makes it very common as a “hard disc replacement” in small devices, such as digital audio players or digital cameras. With regard to reading, flash and MRAM have very similar power requirements, whereas, for writing/rewriting, flash is rewritten using a large pulse of voltage (about 10V) that is stored up over time in a charge pump, which is both power hungry and time consuming. In addition, the current pulse physically degrades the flash cells, which means that a flash memory can only be written to some finite number of times before it must be replaced. In contrast, MRAM requires only slightly more power to write than read, and no change in the voltage, eliminating the need for a charge pump. This leads to a much faster operation, lower power consumption and indefinitely long “live time” for MRAM in comparison with flash memory.
Generally, MRAMs need less “settling time” because MRAM operation is based on measuring voltages rather than charges or currents as in DRAM operation. Even in comparison to flash memory, significant differences appear such that write times of MRAM devices are even thousands of times faster than write times of flash memory devices. In this regard, the only memory technology that presently may compete with MRAM in terms of performance may be static RAM (SRAM). However, an SRAM memory cell consists of a series of transistors arranged in a flip-flop, typically four or six transistors, such that the integration density is lower when compared to DRAM, flash memory and MRAM.
Therefore, although MRAM is not quite as fast as SRAM, it may allow for higher integration densities and is therefore even interesting in applications that employ SRAM technology, that is, applications with very low power requirements.
Overall, MRAM has similar performance to SRAM, similar density to DRAM, but much lower power consumption than DRAM, and is much faster and suffers no degradation over time in comparison to flash memory. It is this combination of features that makes MRAM attractive as the “universal memory” able to replace SRAM, DRAM and flash.
Turning to the basic design of a conventional MRAM memory cell, a so-called “magnetic tunnel junction” (MTJ) is used to form the memory cell structure, which is controlled by a transistor as in DRAM cell structures. Generally, the MTJ is formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer acting as a tunnel barrier. In an MTJ, one of the two plates is configured as a permanent magnetic set to a particular polarity, commonly referred to as “the magnetic pinned layer,” while the other plate is configured such that its magnetization can be changed to a magnetization direction parallel or anti-parallel relative to the magnetization of the magnetic pinned layer, this other layer being commonly referred to as the “magnetic free layer.” This configuration is also known as a spin valve and represents the simplest structure for an MRAM bit. An MRAM memory device may be built from a grid of such “cells.”
In MRAM cells as described above, a reading operation may be accomplished by measuring the electrical resistance over a cell, wherein a particular cell is typically selected by powering the associated transistor, switching current from a supply line through the cell to ground. The effect one makes use of is as follows: due to the magnetic tunnel effect, the electrical resistance of the cell changes based on the orientation of the fields in the magnetic pinned layer and the magnetic free layer. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the magnetization polarity of the writable plate. Typically, if the two magnetic plates have the same polarity, this may be considered to mean “1”, while if the two plates are of opposite polarity, the resistance will be higher indicating “0”.
A writing process for writing data to an MRAM cell may be performed in different ways. In one writing technique (classic technique′), each cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through the write lines, an induced magnetic field is created at the junction and is picked up by the magnetic free layer. This technique suffers from several drawbacks because it requires a fairly substantial current to generate the field and makes it less interesting for low power uses. Furthermore, upon scaling down the cell in size, the risk of the induced field overlapping adjacent cells over a small area increases and, therefore, the risk of false writes increases. Accordingly, a fairly large minimum size is necessary for this type of cell.
In accordance with another technique, spin transfer torque (STT) or spin transfer switching is employed by using spin aligned (“polarized”) electrons to directly torque the domains. Specifically, if the electrons flowing into a magnetic layer have to change their spin, this will develop a torque that will be transferred to the nearby layer. Accordingly, the amount of current needed to write the cells may be lowered, making it about the same as the read process.
There are concerns that the ‘classic’ type of MRAM cell will have difficulty at high densities due to the amount of current needed during writing, a problem that STT avoids. For this reason, the STT proponents expect the technique to be used for devices of 65 nm and smaller. The downside is the need to maintain spin coherence. Overall, the STT requires a comparatively low write current when compared to the classic write technique. For STT-MRAMs, scalability is not an issue because the current required in STT switching can be reduced with the device size.
In general, the design of an STT-MRAM cell at high integration density is required to fulfill the following requirements. For the first requirement, it is important to have a large signal so that the two states (low resistance and high resistance) could be well separated. The second requirement for a functional STT-MRAM is that it have a low resistance or, more specifically, the product of the resistance and the junction area (RA) be low (where the parameter A is the area of the device). It is relatively easy to achieve a high difference between low resistance and high resistance by increasing the tunnel barrier thickness, but the junction area (RA) will increase almost exponentially. The value of the junction area (RA) is actually dictated by the value of the breakdown voltage of the tunnel barrier which is the critical voltage that can be applied to the MTJ before it becomes damaged. Accordingly, the switching of the magnetic free layer should occur before reaching the breakdown voltage. The third criteria relates to thermal stability demanding that information stored in an MRAM is stable for a period of ten years. The fourth key parameter in STT-MRAM techniques is to limit the switching current according to the size of the transistor used because smaller switching current helps to achieve large storage capacity for the STT-MRAM with scaled transistors. Finally, it is highly desirable to achieve the above requirements for STT-MRAM techniques with a suitable fabrication process that does not compromise CMOS integration.
Furthermore, with regard to the magnetic pinned layer and the magnetic free layer, two basic concepts exist. According to the first concept, the magnetic layers can have an in-plane magnetization wherein the magnetic layers have a magnetization perpendicular to a thickness direction of the magnetic layers. Alternatively, according to the second concept, the magnetic layers have a magnetization parallel to the thickness direction of the magnetic layers. While MRAM technology using the first concept is mature and in production for 90 nm, MRAM cells using the second concept, i.e., magnetic layers with parallel magnetization, are still in the research phase. It should be noted that the magnetic material engineering is very different for the two concepts. With regard to the first concept, i.e., magnetic layers with in-plane (perpendicular) magnetization, this concept is not scalable below 40 nm because the thermal stability of the magnetization (the temperature induced switching of the magnetization) scales with the MRAM element size and reaches its lowest limit at about 40 nm. Furthermore, thermal stability of MRAM made according to the second concept (with parallel magnetization) scales with the shape anisotropy of the MRAM cell geometry (which is of elliptical shape for in-plane magnetic layers), resulting in additional area needed for MRAM elements. At present, MRAMs made according to the second concept according to which the magnetization is parallel to the thickness direction of the magnetic layers, appear to be the better option for technologies of 20 nm and below as the intrinsic energy barrier (magnetic anisotropy) for switching the magnetization is larger and does not depend on the MRAM cell geometry. However, the materials with perpendicular magnetic anisotropy as used in the second concept are more expensive and critical to handle during the fabrication processes.
In view of the above discussion, it is desirable to provide a functional MRAM concept with in-plane magnetization at smaller scales, particularly at scales smaller than 40 nm.